PCI Express (PCIe) Gen 1 to Gen 3 Architecture

We will discuss the details of the PCI Express protocol stack for Express devices, including the three protocol layer functions and formats and their configuration requirements. You will learn about the latest protocol enhancements that are required to support the new Gen3 speed of 8GT/s. These include the 128/130b encoding schemes, block formats, and new equalization procedures.

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In this PCI Express (PCIe) Architecture online training course, you will learn about the key features of the PCI-SIG‘s specifications from PCI foundations all the way to, and including, the latest version 3.0 changes/enhancements. You will learn about Legacy and native PCI Express devices and how the new features of PCIe can be supported whilst still providing compatibility with legacy PCI devices and software.

We will discuss the details of the PCI Express protocol stack for Express devices, including the three protocol layer functions and formats and their configuration requirements. You will learn about the latest protocol enhancements that are required to support the new Gen3 speed of 8GT/s. These include the 128/130b encoding schemes, block formats and new equalization procedures.

We will also overview the new features added to the PCIe specification – such as Multicast, Access Control Services, Alternative Routing ID Interpretation, Advanced Error Reporting, Address Translation Services, Optimized Buffer Flush/Fill, Latency Tolerance Reporting, M-PCIe and Readiness Notifications. We will also discuss Signal Integrity and the challenges that the new speeds of PCIe bring to board layout, as well as I/O virtualization and multi host resource sharing.

In This Course You Will Learn:

  • Explain PCI Express fabric topology, the terms and definitions
  • Identify the PCI Express protocol including layer definitions and layer relationships
  • List the Traffic types defined by PCI Express and the meaning and how packets are created and routed
  • Define the PCI Express configuration mechanism used in plug and play.
  • Identify the compatibility requirements needed to support PCI and PCI-X as well as how the PCI Express enhanced features are accessed and implemented.
  • Discuss the parallel/serial paradigm shift and PCI Express capabilities relative to other serial hardware/software architects
  • Appreciate the reasons for the new encoding procedures and the subsequent techniques needed when operating at 8GT/s
  • Be able to recognize some of the new features that are being introduced to PCIe through engineering change notifications and recognize the benefits these will bring to the PCIe fabric.


Participants should have an understanding of how parallel and serial bus systems are used in PC systems and although knowledge of the PCI and PCIe specifications is beneficial it is not a requirement.

Module 00: PCI Express Gen 1 to Gen 3 Architecture – Course Introduction

Module 01:  PCI Evolution

  • PC I/O History
  • PCIe Compatibility
  • PCIe Features

Module 02:  PCI Commands, Bus Operations and Device Types

  • PCI Commands and Transactions
  • PCIe Packets
  • PCIe Waveform
  • PCI Commands, Bus Operations and Device Types Quiz

Module 03: Bridges, Switches, Arbitration and Interrupts

  • PCI Arbitration
  • PCIe Switch Structure
  • Interrupts

Module 04: Error Handling, Signaling Environments and Address Spaces

  • Error Reporting Methods
  • Link Attributes
  • Understanding Bandwidth
  • Configuration Headers
  • Bridge, Switches and Address Spaces Quiz

Module 05: Configuration Space

  • Configuration Space Model
  • PCIe Capability Structure
  • Root Complex

Module 06: Bridge Discovery

  • Switch Config Space Compatibility
  • PCI Type 1 to Type 0 Conversion
  • Configuration Space Probing
  • Bridge Discovery and Capability Structure Quiz

Module 07: Configuration Methods

  • Bus Enumeration
  • Base Limit Registers
  • Address Routing
  • ID Routing

Module 08: Configuration Registers

  • Register Attributes
  • Header Types
  • Extended Capability Structures
  • Optional Registers
  • Enumeration Workshop and Configuration and PCIe Routing Quiz

Module 09: Transaction Layer Protocol Part 1

  • Overview of TLP Transactions
  • TLP Packet Components
  • TLP Packet Components
  • TLP Headers

Module 10: Transaction Layer Protocol Part 2

  • TLP Fmt Encoding
  • TLP Attributes
  • Error Poisoning
  • Data Payloads
  • Transaction Descriptor

Module 11: Transaction Layer Protocol Part 3

  • Byte Enable Rules
  • TLP Addressing
  • Completion Rules
  • Transaction Layer Protocol Quiz

Module 12: MSI and Messages

  • Message Codes and Rules
  • Error Signaling
  • Post and Non-Posted Transactions

Module 13: Transaction Ordering, Virtual Channels and Flow Control

  • PCIe Ordering Rules
  • Virtual Channel Mapping
  • PCIe Flow Control Overview
  • Completion Time Out
  • Transaction Ordering, Virtual Channels and Flow Control Quiz

Module 14: Data Link Layer Part 1

  • DLLP Construction
  • DLL Control
  • Initialization Flow Control

Module 15: Data Link Layer Part 2

  • DLLP Header
  • DLL Services
  • DLL Flow Control

Module 16: Data Link Layer Part 3

  • Normal Operations
  • TLP Conditioning
  • Sequence Numbering
  • Replay Timer
  • Data Link Layer Quiz

Module 17: Physical Layer Part 1

  • Sub-Block Overview
  • Scrambling
  • Encoding
  • Link Initialization

Module 18: Physical Layer Part 2

  • PCIe Signaling
  • Byte Striping
  • Lane Assignments
  • Polarity and Lane Reversal
  • Physical Layer Quiz

Module 19: Serial Versus Parallel Communications

  • Review of Parallel Systems
  • Serial Signaling
  • Graphics Review
  • Layered Protocols Stacks OSI

Module 20: Layered Protocols Stacks PCIe

  • PCIe Layers
  • Error Detection Within Layers
  • PCIe Mapping Comparison
  • PCIe and Switches
  • Signaling, Stacks and Switches Quiz

Module 21: Serial Protocol Analyzers

  • Test Verification Tools
  • Serial Testing
  • Protocol Analyzer Characteristics
  • PCIe Compliance

Module 22: Link Training and Status State Machine (LTSSM)

  • LTSSM Overview
  • LTSSM Link Initialization
  • LTSSM Sub-States
  • Link Speed Change

Module 23: LTSSM Power Management

  • PCIe Link PM State Diagram
  • PCIe PM Link States
  •  PCI Power Management Compatibility
  • Transitioning to Low Power States
  • LTSSM Quiz

Module 24: Virtual Channels Differentiated Services

  • Virtual Channels Overview
  • Traffic Classes
  • Arbitration Methods
  • Register Sets Details

Module 25: Virtual Channels Examples

  • Arbitration Examples
  • Traffic Class Virtual Channel Mapping Example
  • Traffic Class Filtering
  • Link Multiplexing
  • Isochronous Traffic Example
  • Virtual Channels Quiz

Module 26: System Issues and Features

  • Initialization and Enumeration Review
  • Error Signaling and Logging
  • Error Classifications
  • PCIe Resets

Module 27: Hot Plug Power Management and Interrupts

  • Hot Plug Elements
  • Hot Plug Card Removal and Insertion Example
  • PCIe Power Management
  • PCIe Interrupts
  • Handling Legacy Interrupts
  • Message Signal Interrupts
  • Hot Plug,  Power Management and Interrupts Quiz

Module 28: Electrical and Mechanical Requirements

  • Card Electro Mechanical Specification Overview
  • Adding Cards
  • Card Interoperability
  • Card Form Factors
  • Routing Considerations
  • PCIe Clocking

Module 29: I/O Virtualization in PCIe Overview Part 1

  • IOV Definitions
  • Connecting Multiple Hosts Together
  • Options and Issues

Module 30: I/O Virtualization in PCIe Overview Part 2

  • Muli-Root  (MR-IOV)
  • Single-Root (SR-IOV)
  • Non Single-Root IOV
  • I/O Virtualization in PCIe Quiz

Module 31: PCIe Gen3 Protocol Enhancements

  • Protocol Overview
  • Compatibility
  • Encoding Revision
  • Gen3 Encoding
  • Data Blocks
  • Framing Tokens

Module 32: Gen3 Block Alignment and Scrambling

  • Ordered Set Blocks
  • Block Phases
  • Framing Requirements
  • Block Framing Examples
  • Scrambling
  • Error Detection and Recovery
  • Gen3 Protocol and Encoding Quiz

Module 33: LTSSM Updates

  • LTSSM Review
  • Recovery and Support for Gen3
  • Gen3 Equalization Training Sequence
  • Gen3 Equalization Phase
  • Testability Features

Module 34: Gen3 Equalization Phase

  • Gen3 Equalization
  • Gen3 Equalization Phase Details
  • Gen3 Equalization Phase Summary
  • Gen3 Equalization Phase Quiz

Module 35: Gen3 Signal Integrity Overview

  • Gen3 Signal Challenges
  • Gen3 Filtering and Equalization
  • Board Layout Considerations
  • Gen3 Signal Integrity Quiz

Module 36: PCIe Gen2/3 Protocol Enhancements Overview Part 1 

  • Multicast
  • Access Control Services
  • Alternative RoutingID Interpretation (ARI)
  • AER

Module 37: PCIe Gen2/3 Protocol Enhancements Overview Part 2 

  • Address Translation Services
  • Optimized Buffer Flush/Fill (OBFF)
  • Latency Tolerance Reporting (LTR)
  • Downstream Port Containment (DPC)
  • Separate Refclk with Independent SSC (SRIS)
  • M-PCIe
  • Readiness Notifications (RN)
  • PCIe Gen2/3 Protocol Enhancements Quiz

1 Year Access

Delivery Type: The Course is taken online
Length of Access: 1 year
Features: 24/7 Access, Real Instructors, Classroom Materials and Exercise Guides.

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Meet Your Instructor

Paul Baron

Paul Baron has more than 30 years’ experience working in the semiconductor industry specializing in I.C Design, Applications Engineering and Engineering Management for companies such as Motorola, Cadence, PLX and Actel FPGA specialist ACAL. During this time he has developed and presented many customer and distributor training courses relating to PCI Express, DAS/NAS, System On Chip and FPGA design. Prior to starting his own company in 2013 he spent five years working for PLX as a European Field Applications Engineer providing technical design-in support for their world-class PCI Express switch, bridge and storage products. He holds a BSc in Electronics and is a Member of the Institute of Engineering and Technology (MIET).

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  • Student Guide
  • Quiz Guide
  • Quiz Answer Guide
  • Enlarged Slides

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  • Course Survey

Course Transcript

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Letter of Course Attendance

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